1. Field of the Invention
The present invention relates to an apparatus and a method for scaling a dynamic bus clock. More particularly, the present invention relates to an apparatus and a method for scaling a bus clock frequency of a digital system by considering use of an on-chip bus.
2. Description of the Related Art
In a synchronous digital system, one or more master modules and one or more slave modules transmit and receive data based on a bus.
FIG. 1 illustrates a bus in a conventional digital system.
Referring to FIG. 1, one or more master modules 100-1, 100-2, through 100-n transmit and receive data to and from one or more slave modules 110-1, 110-2, through 110-m through a bus 120. The master modules 100-1 through 100-n, the slave modules 110-1 through 110-m, and the bus 120 use a fixed bus clock BUS_CLK generated by a clock generator 130. The clock generator 130 generates a maximum frequency to achieve the highest performance of the digital system.
To reduce power consumption, the digital system adopts a Dynamic Voltage and Frequency Scaling (DVFS) technique.
Using the DVFS technique, the digital system changes the entire frequency of a Central Processing Unit (CPU) or the digital system by measuring activity information of a main processor CPU.
However, the DVFS technique regulates voltage and frequency of the CPU by measuring only the activity information of the CPU. Accordingly, the digital system merely reduces the power of the CPU by changing the frequency of the CPU using the DVFS technique.
When the entire frequency of the digital system is changed using the DVFS technique and there exists a master module requiring an independent bus bandwidth besides the CPU, the performance of the digital system may be degraded due to the CPU-centered DVFS technique.